Printed circuit board assembly time minimisation using a novel Bees Algorithm

Castellani, Marco, Otri, Sameh and Pham, Duc Truong 2019. Printed circuit board assembly time minimisation using a novel Bees Algorithm. Computers and Industrial Engineering 133 , pp. 186-194. 10.1016/j.cie.2019.05.015

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Abstract

This paper presents a novel version of the Bees Algorithm customised to solve combinatorial optimisation problems. This version was created to minimise assembly time in the manufacturing of printed circuit boards using a machine of the moving-board-with-time-delay type, and optimising the feeder arrangement and machine component placement sequence. The local search procedure of the standard Bees Algorithm was modified to include five new operators for combinatorial optimisation. The customised Bees Algorithm was first tested on the related travelling salesman problem, where it excelled in terms of performance and efficiency compared to three state-of-the-art optimisation methods. It was then applied to a well-known moving-board-with-time-delay benchmark problem, where it performed favourably in comparison to the state-of-the-art in the literature, achieving fast and consistent solutions.

Item Type:	Article
Date Type:	Publication
Status:	Published
Schools:	Engineering
Publisher:	Elsevier
ISSN:	0360-8352
Date of Acceptance:	10 May 2019
Last Modified:	04 Jun 2019 10:30
URI:	https://orca.cardiff.ac.uk/id/eprint/123065

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